LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;

entity cup_ram5 is port (
clk : in std_ulogic;
rst :in std_ulogic;
cup1_beginning :in std_ulogic;
state1 : in std_ulogic;
u :in  std_ulogic_vector(15 downto 0);
ch :in  std_ulogic_vector(15 downto 0);
sig : in std_ulogic_vector(15 downto 0);
count_cr :in  std_ulogic_vector(7 downto 0);
count_cw :in  std_ulogic_vector(7 downto 0);
count_vr : in std_ulogic_vector(6 downto 0);
count_vw : in std_ulogic_vector(6 downto 0);
cup_enable : in std_ulogic;
vup_enable : in std_ulogic;
wb_clk : in std_ulogic;
wenr    : in  std_ulogic_vector(7 downto 0);
--wenw    :  in std_ulogic_vector(7 downto 0);
wb_addr : in std_ulogic_vector(7 downto 0);
wb_data :in  std_ulogic_vector(7 downto 0);
e_temp :out  word32_array;
llrq :in word32_array
);
end entity ;
architecture rtl of cup_ram5 is  
        component memorybank is
          port(
		          clk: in std_ulogic;
		          flag: in std_ulogic;
		          flag1: in std_ulogic;
		          flag2: in std_ulogic;
		          addr_cr: in std_ulogic_vector(7 downto 0);
		          addr_cw: in std_ulogic_vector(7 downto 0);
		          addr_vr: in std_ulogic_vector(6 downto 0);
		          addr_vw: in std_ulogic_vector(6 downto 0);
		          e_in: in std_ulogic_vector(15 downto 0);
              e_out: out std_ulogic_vector(31 downto 0);
	            q_in: in std_ulogic_vector(31 downto 0);
		          q_out: out std_ulogic_vector(15 downto 0)
		);
		end component;

component cup is
port(
    clk,reset: in std_ulogic;
    initflag:in std_ulogic;   ---------
    flag:in std_ulogic;       ---------
    flag1:in std_ulogic;      ---------
    u: in std_ulogic_vector(15 downto 0);  -----
    sigma: in std_ulogic_vector(15 downto 0);  ----
    chanx: in std_ulogic_vector(15 downto 0);  ----
    q_1,q_2,q_3,q_4,q_5,q_6,q_7,q_8: in std_ulogic_vector(15 downto 0);----
    llrr_w1,llrr_w2,llrr_w3,llrr_w4,llrr_w5,llrr_w6,llrr_w7,llrr_w8: out std_ulogic_vector(15 downto 0)
   
    );
end component ;
component delay is 
  port(
clk     : in std_ulogic;
delay_in   : in std_ulogic_vector(7 downto 0);
delay_out  : out std_ulogic_vector(7 downto 0)
		     );
end component;
component LVT_CLKLAHAQVHSV4   is 
  port (
     Q : out std_ulogic;
     E : in std_ulogic;
     TE : in std_ulogic;
     CK : in std_ulogic
    );
  end component ;
  component rf256x8mux4 is 
  port ( 
    qA: out std_logic_vector(7 downto 0);
    CLKA: in std_logic;
    CENA: in std_logic;
    AA: in std_logic_vector(7 downto 0);
    CLKB: in std_logic;
    CENB: in std_logic;
    AB: in std_logic_vector(7 downto 0);
    DB: in std_logic_vector(7 downto 0)
      );
  end component;
signal ad ,ads : word8_array;
signal q_temp : word16_array;
signal llrr : word16_array;
signal sigma : word16;
signal gclk: std_ulogic;
signal cr_en : std_logic_vector(7 downto 0);
signal ab : std_logic_vector(7 downto 0);
signal db : std_logic_vector(7 downto 0);
signal cena : std_logic;
signal aa :std_logic_vector(7 downto 0);
signal qa0,qa1,qa2,qa3,qa4,qa5,qa6,qa7 :std_logic_vector(7 downto 0);
begin
  process (clk)
    begin
    if clk'event and clk = '1' then 
      if state1 = '0' then 
        sigma <= sig;
      end if;
    end if;
  end process;
    g: LVT_CLKLAHAQVHSV4   port map(
                    CK => clk ,
                    Q =>  gclk,
                    E => cup_enable,
                    TE => '0'
                   );
  b1 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(0),
                               addr_cw  =>  ad(0),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(0),
                               q_in     =>  llrq(0),
                               q_out    =>  q_temp(0),
                               e_out    =>  e_temp(0)); 
    b2 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(1),
                               addr_cw  =>  ad(1),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(1),
                               q_in     =>  llrq(1),
                               q_out    =>  q_temp(1),
                               e_out    =>  e_temp(1)); 
  b3 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(2),
                               addr_cw  =>  ad(2),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(2),
                               q_in     =>  llrq(2),
                               q_out    =>  q_temp(2),
                               e_out    =>  e_temp(2)); 
    b4 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(3),
                               addr_cw  =>  ad(3),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(3),
                               q_in     =>  llrq(3),
                               q_out    =>  q_temp(3),
                               e_out    =>  e_temp(3)); 
      b5 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(4),
                               addr_cw  =>  ad(4),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(4),
                               q_in     =>  llrq(4),
                               q_out    =>  q_temp(4),
                               e_out    =>  e_temp(4)); 
                                 b6 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(5),
                               addr_cw  =>  ad(5),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(5),
                               q_in     =>  llrq(5),
                               q_out    =>  q_temp(5),
                               e_out    =>  e_temp(5)); 
                                 b7 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(6),
                               addr_cw  =>  ad(6),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(6),
                               q_in     =>  llrq(6),
                               q_out    =>  q_temp(6),
                               e_out    =>  e_temp(6)); 
                                 b8 :  memorybank port map( clk      =>  clk,
                               flag     =>  '1',
                               flag1    =>  cup_enable,
                               flag2    =>  vup_enable,                             
                               addr_cr  =>  ads(7),
                               addr_cw  =>  ad(7),
                               addr_vr  =>  count_vr,
                               addr_vw  =>  count_vw,
                               e_in     =>  llrr(7),
                               q_in     =>  llrq(7),
                               q_out    =>  q_temp(7),
                               e_out    =>  e_temp(7)); 
  
  c11:cup  port map(
                      clk=>gclk,
                      reset =>rst,
                      initflag=>cup1_beginning,
                      u=>u,
                      sigma=>sigma,
                      chanx=>ch,
                      flag=>'1',
                      flag1=>cup_enable,
                      q_1=>q_temp(0),
                      q_2=>q_temp(6),
                      q_3=>q_temp(2),
                      q_4=>q_temp(5),
                      q_5=>q_temp(4),
                      q_6=>q_temp(3),
                      q_7=>q_temp(1),
                      q_8=>q_temp(7),
                      llrr_w1=>llrr(0),
                      llrr_w2=>llrr(6),
                      llrr_w3=>llrr(2),
                      llrr_w4=>llrr(5),
                      llrr_w5=>llrr(4),
                      llrr_w6=>llrr(3),
                      llrr_w7=>llrr(1),
                      llrr_w8=>llrr(7));



d0 : delay port map(clk   => clk ,
            delay_in => ads(0),
             delay_out => ad(0));
             d1 : delay port map(clk   => clk ,
            delay_in => ads(1),
             delay_out => ad(1));
             d2 : delay port map(clk   => clk ,
            delay_in => ads(2),
             delay_out => ad(2));
             d3 : delay port map(clk   => clk ,
            delay_in => ads(3),
             delay_out => ad(3));
             d4 : delay port map(clk   => clk ,
            delay_in => ads(4),
             delay_out => ad(4));
             d5 : delay port map(clk   => clk ,
            delay_in => ads(5),
             delay_out => ad(5));
             d6 : delay port map(clk   => clk ,
            delay_in => ads(6),
             delay_out => ad(6));
             d7 : delay port map(clk   => clk ,
            delay_in => ads(7),
             delay_out => ad(7));
           
 cr1 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(0), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa0
                             );   
cr2 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(1), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa1
                             ); 
cr3 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(2), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa2
                             );    
 cr4 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(3), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa3
                             );   
cr5 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(4), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa4
                             ); 
cr6 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(5), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa5
                             );                                
cr7 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(6), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa6
                             );   
cr8 : rf256x8mux4 port map (CLKB => wb_clk ,
                            CENB => cr_en(7), 
                            AB => ab ,
                            DB => db ,
                            CLKA => clk ,
                            CENA => cena ,
                            AA => aa ,
                            QA => qa7
                             );                              
                             
  ab <= std_logic_vector(wb_addr);
  db <= std_logic_vector(wb_data);
  cena <= not cup_enable ;
  aa <= std_logic_vector(count_cr);
  ads(0) <= std_ulogic_vector(qa0);
  ads(1) <= std_ulogic_vector(qa1);
  ads(2) <= std_ulogic_vector(qa2);
  ads(3) <= std_ulogic_vector(qa3);
  ads(4) <= std_ulogic_vector(qa4);
  ads(5) <= std_ulogic_vector(qa5);
  ads(6) <= std_ulogic_vector(qa6);
  ads(7) <= std_ulogic_vector(qa7);                           
  cr_en(0) <= not wenr(0) ;
  cr_en(1) <= not wenr(1) ;                                                                      
  cr_en(2) <= not wenr(2) ;
  cr_en(3) <= not wenr(3) ;
  cr_en(4) <= not wenr(4) ;
  cr_en(5) <= not wenr(5) ;
  cr_en(6) <= not wenr(6) ;
  cr_en(7) <= not wenr(7) ;                                   
end rtl;